1. Field of the Invention
The invention generally relates to the field of integrated circuit devices. More particularly, the invention relates to a memory device in which a memory read operation is accomplished by comparing two differential voltage signals provided by a column of memory cells.
2. Description of Related Art
Typical semiconductor memories include an array of memory cells arranged in columns and rows. Each column includes a set of memory cells connected to a node called a bit line, or possibly to several bit lines. Each row includes a set of memory cells connected to a common node called a word line, or possibly to several word lines. Each memory cell is associated with a unique combination of a word line and a bit line. Enablement of a row by a word line connects each memory cell in that row to its respective bit line or bit lines allowing data stored therein to be read or output. In state of the art devices, there are typically a large number of memory cells coupled to the bit line or lines of each column. Accordingly, the capacitance which the memory cell must drive is large and the bit lines charge and discharge slowly. Designers typically compensate for this inherent slowness by providing sense amplifiers for sensing small changes on the bit line or bit lines and amplifying the small changes into useful signals.
One broad class of such memories includes an array in which each column of cells is connected to two bit lines. Data is read from the memory as a differential voltage that is driven onto the bit lines by a selected memory cell. The differential voltage is amplified by a sense amplifier to levels which represent the logic value 1 or the logic value 0. The amplified voltage signals are then employed to perform logical functions using digital logic circuits. The differential nature of the voltage sensing and amplification achieves reduced access time and immunity from external sources of noise via common mode rejection. Thus, the use of a differential memory cell connected to a pair of bit lines allows faster read operations than a "single-ended" memory cell which is connected only to a single bit line.
Such memories are generally implemented either in N-Channel Metal Oxide Semiconductor (NMOS), Complementary Metal Oxide Semiconductor (CMOS) or Bipolar--CMOS (BiCMOS) integrated circuits. With these technologies, entire memories are placed on a single integrated circuit either alone or in combination with other digital or analog devices. Cost savings in material and in device interconnection labor is achieved. Moreover, integration on a single substrate guarantees a high degree of device matching which is necessary for manufacture of reliable differential components. However, a differential memory cell requires additional silicon die area than a single-ended memory cell, such as the single transistor, single capacitor Dynamic Random Access Memory (DRAM) cell. Nevertheless, the speed and noise immunity advantages gained by the differential memory cell typically compensate for the increased consumption of silicon die area.
Thus, a differential memory allows data to be read faster than a single-ended memory. Various techniques have been developed for sensing the differential voltage and amplifying the voltage. One simple method uses a CMOS inverter connected to either of the bit lines to generate a full rail swing on the output. This technique is limited to differential memories with very few rows. In larger memories having many rows, a significant bit line capacitance loads the bit lines. The significant bit line capacitance prevents the CMOS inverter from generating a full rail swing on the output promptly. An improved method for large arrays uses a differential amplifier or several stages of static differential amplifiers to generate a larger useful signal from the small bit line differential The principal disadvantages of this technique are that each amplifier consumes direct current to operate and requires significant effort for proper design and characterization over all conditions of temperature, voltage, and manufacturing variability. Design improvements have helped to reduce these difficulties but, in substantial part, the difficulties remain.
For synchronous differential memories which are enabled by an externally provided clock edge, a more simple and elegant technique has prevailed. A read cycle begins by enabling a selected word line which interconnects all memory cells of one row. Each memory cell is configured such that one of the two bit lines in each column will begin to discharge, while the other remains at a precharge voltage, usually the high voltage rail. When a sufficient voltage differential is generated between the two bit lines, the sense amplifier samples the differential and rapidly amplifies the differential to yield a signal defined by two outputs with one output at ground and the other at a high voltage rail, such sense amplifiers are referred to as regenerative or dynamic sense amplifiers in common industry usage, but are herein referred to as delay-triggered sense amplifiers.
A minimum differential must be developed on the bit lines before the sense amplifier can reliably amplify it. In other words, a suitable "margin" must be developed within the differential signals before the sense amplifier can reliably amplify the differential. The amount of any necessary margin is defined by physical asymmetries in the circuits, noise couplings and sensitivity to alpha particle strikes. Alpha particle strikes, for example, can cause a reversal in the voltage differential such that, when the reversed differential is amplified, the original polarity of the differential is lost resulting in the output of erroneous data. A sufficient margin substantially guarantees that such an event will not occur.
To allow a necessary voltage differential to be developed on the bit lines before the sense amplifier samples and amplifies the differential, activation of the sense amplifier is typically delayed. In other words, the sense amplifier is not activated simultaneously with the memory cells. Rather, the sense amplifiers are activated sometime after the memory cells are activated, thereby allowing the memory cells to generate a sufficient voltage differential across the bit lines. In some differential memory devices, a simple inverter delay chain, or equivalent, is provided to delay activation of the sense amplifier following the activation of the memory cells by a read enable signal. However, circuits of the inverter delay chain will behave differently from the circuits of the memory cells under different conditions of temperature, supply voltage, and manufacturing variability, causing reliability issues which in turn require guardbanding and a corresponding slower access speed. In other words, the actual bit line differential caused by the inverter delay chain may differ from circuit to circuit. To ensure that a sufficient amount of delay is provided under all conditions to thereby ensure a sufficient voltage differential margin, the time delay is typically increased beyond the minimum delay that would otherwise be necessary, thereby yielding overall slower access of data from the memory circuit. As an alternative to inverter delay chains, some memory circuits employ a dummy word line which load is matched to circuits of the memory cells. The signal routed to the dummy word line is then employed as a sense amplifier enable signal for triggering operation of the sense amplifiers. With this arrangement, any process or temperature variation in the time delay of a signal transmitted through the dummy word line will also match the variation of the corresponding time delay of the signals routed through the memory cells. Hence, no significant difference in bit line differential will occur due to word line delay regardless of differences in temperature, voltage or manufacturing process. In some memory circuits, the sense amplifier enable signal is also routed through a dummy bit line for improved matching characteristics.
Although the use of the dummy word lines or dummy bit lines helps eliminate the need to increase the delay time beyond the minimum amount necessary, it would be helpful to further reduce the minimum delay time as well.
An example of differential memory of the type described above is illustrated in FIG. 1. More specifically, FIG. 1 illustrates a memory device 10 having a memory array 12, a row decoder 14, a column decoder 16 and a sense amplifier 18. Array 12 includes an array of individual SRAM memory cells 20. In use, a row selection signal is received and decoded by row decoder 14 which outputs a word line signal on one of a set of word lines 22 connected to all memory cells of the corresponding row of array 12. The word line signal causes each cell of the row to begin to output the binary value stored therein as a differential voltage signal along a pair of differential bit lines 24 and 26 interconnecting each column of memory cells. In this particular example, each pair of bit lines 24 and 26 are connected to a corresponding sense amplifier 30 within sense amplifier array 18. However, this is not the generate case since several columns may be multiplexed into a single sense amplifier via column selects. As noted above, the sense amplifiers are not immediately activated. Rather, the sense amplifiers are triggered by a sense amplifier enable signal 36 provided by a delay unit 32. Delay unit 32 receives a word line enable 34 from row decoder 14 at the same time the memory cells received the word line signal. The delay unit outputs the delayed word line enable signal as a sense amplifier enable signal 36 to the sense amplifiers 30. As noted above, the delay in triggering operation of the sense amplifiers is provided to ensure that the memory cells have sufficient time to establish a minimum voltage differential before the sense amplifiers begin to operate. This helps prevent the sense amplifiers from sensing and amplifying an erroneous differential, perhaps caused by an alpha particle strike or other noise source, and thereby helps prevent reading incorrect data. Although not separately shown in FIG. 1, delay unit 32 may include a dummy word line having a set of dummy memory cells whose loads are physically matched to the cells of array 12 to minimize any time delay skew that may occur as a result of temperature, manufacturing or process variations.
Thus, sense amplifiers 30 are not activated until a sense amplifier enable signal is received along line 36. Furthermore, the column decoder 16 will, in the general case, select one of several bit line pairs which is to be multiplexed into the sense amplifier. In this manner, one may choose to output only a subset of the logical values stored in each word line. To this end, the column decoder receives one or more column selection signals. These selection signals activate pass gates which permit the differential voltage on one bit line pair to pass into the sense amplifier. Only one pair of pass gates will be activated by their selection signal for each sense amplifier in question. All other selection signals will remain unasserted. FIG. 1 shows the case in which two bit line pairs are multiplexed into a single sense amplifier. A set of bit pair select lines 37 selects one pair of bit lines within each sense amplifier. If one desires to read N logical values from the array 12 in a given read cycle, then N sense amplifiers are required. A separate sense amplifier is required for each column of array 12 only if it is necessary to output all bits from an entire row of array 12 simultaneously.
Thus, with this arrangement, within each read cycle one entire row of memory cells are activated and corresponding differential bit lines are charged or discharged accordingly. After a delay period provided by delay unit 32, the sense amplifiers of array 18 are triggered to sense and amplify the differential voltage between a subset of the pairs of bit lines as specified by the column decode decorder.
FIGS. 2 and 3 illustrate suitable SRAM cells 40 and 41, respectively. SRAM cell 40 of FIG. 2 includes a pair of cross-coupled inverters connected between a power supply and ground. Each inverter includes a P-channel device and a N-channel device. Output nodes of the cross-coupled inverters are connected through N-channel pass gate devices 42 and 43 to respective bit lines 24 and 26. A word line 22 is connected to the gates of the N-channel pass devices. With this arrangement, when the word line is pulled high, the cross-coupled inverters begin to discharge one of the two bit lines creating the aforementioned voltage differential.
The SRAM cell 41 of FIG. 3 is similar to that of FIG. 2 but, rather than including a pair of P-channel devices, a pair of highly resistive loads are employed. SRAM cell 41 operates in the same manner as that of FIG. 2. The use of resistors, rather than P-channel devices, allows the SRAM cell to be configured with a somewhat smaller size. On the other hand, because resistors are employed, rather than P-channel devices, a greater quiescent current is drawn. In either embodiment, during operation, one of the N-channel pass devices 44 or 45 or alternatively pass devices 42 or 43 draws a current of I from the bit line connected thereto whereas the other N-channel pass device draws no current. The current drawn through one of the N-channel devices allows current discharge from the corresponding bit line thereby causing a drop in the voltage of the corresponding bit line.
FIG. 4 illustrates a suitable sense amplifier 30. Sense amplifier 30 has a bistable element embodied by a pair of P-channel devices 52 and 54 and a pair of N-channel devices 56 and 58. Sources of the N-channel devices are tied to a node 60 and driven by sense amplifier enable line 36 through an inverter 62. Sources of the P-channel devices are connected to a positive power supply with respect to ground. Output nodes 64 and 66 of the bistable element are coupled to differential bit lines 24 and 26, respectively, through P-channel pass gates 76 and 78 and drive output lines 68 and 70 through inverters 72 and 74, respectively. Gates of P-channel devices 76 and 78 are and comprise a column select line 80 connected to the column decoder. Figure illustrates the case in which the sense amplifier can be coupled to only a single column. In the general case, a sense amplifier of this type might include multiple pairs of P-channel pass gates in order that it might couple to one of any number of such columns.
With this configuration, node 60 is typically held high by inverter 62 while the sense amplifier enable signal is not active. Accordingly, the bistable element is not activated and no positive feedback occurs within it. Additionally, nodes 64 and 66 are precharged to an equal potential. The precharge elements are not indicated here, but can be implemented in a number of manners. The precharge elements are shut off before the read cycle commences. During this time, a differential between the voltages on the pair of bit lines is developed as a result of operation of one of the SRAM cells of the corresponding column. While the differential voltage is developed, the column select signal is held low, thereby allowing the bit lines to discharge nodes 64 and 66 accordingly. Once a suitable amount of differential voltage is generated, after waiting the aforementioned delay time, the sense amplifier enable signal is switched to high, thereby pulling down node 60 and triggering a race condition between the matched P-channel and N-channel pairs in the bistable element. The race is unequal, however, because of the differential applied to nodes 64 and 66, causing the cross-coupled inverters to quickly reach a state wherein either node 64 is high and node 66 is low or vice versa, depending upon the polarity of the initial differential. In other words, the slight differential between the bit lines is quickly amplified to a rail-to-rail differential between nodes 64 and 66. Inverters 72 and 74 then drive the resulting signals onto corresponding output signals 68 and 70.
Preferably, when the sense amplifier enable signal is activated, the column selection signal is deactivated, thereby decoupling nodes 64 and 66 from bit lines 24 and 26, respectively. Without decoupling, the devices of the bistable element would need to pull down one of the two bit lines from a high voltage to zero. As can be appreciated, within large memory arrays wherein the bit lines are coupled to a large number of memory cells, the capacitance on the bit lines, and therefore, on nodes 64 and 66, is significant. Accordingly, it would be difficult for the bistable element to quickly pull down the voltage on one of the bit lines. By decoupling nodes 64 and 66 from the bit lines, however, the bistable element is thereby decoupled from the bit lines and can operate much more quickly. On the other hand, by decoupling the cross-coupled inverters from the bit lines, the cross-coupled inverters become more vulnerable to noise, such as alpha strikes. In other words, once decoupled, the only noise immunity of the cross-coupled inverters is provided by the capacitance of the components of the sense amplifier which is relatively small. Accordingly, an alpha strike, as mentioned above, can cause a reversal in polarity of the differential obtained on nodes 64 and 66 resulting in an erroneous sense amplifier output signal sense amplifier to output an erroneous signal. Hence, deactivation of the column select signal is delayed beyond the activation of the sense amplifier enable signal by an amount of time sufficient to ensure that an adequate differential is obtained between nodes 64 and 66 before the sense amplifier is activated such that an alpha strike will not cause a change in polarity of those nodes. For a 3-volt circuit, the minimum sufficient voltage differential is typically about 300 millivolts.
Thus, for the sense amplifiers of the type illustrated in FIG. 4, a trade-off occurs between sense amplification speed and reliability. Deactivation of the column decoder is intentionally delayed to help ensure reliability. It would be desirable to provide an improved sense amplification method and apparatus which maintains reliability but allows sense amplification to occur without as long of a delay time.